• 完全兼容最新USB3.1 技术标准
• 支持所有USB 连接器，包括A, B and Type-C
• 支持wire-bonding 及flip-chip封装形式
• 兼容PIPE接口协议
• 支持标准摆幅及低摆幅模式
• 3-tap  可编程前置均衡器（预加重/去加重）
• 接收端内置自适应线性均衡器
• 内置1-tap  判决反馈均衡器
• 内建自测机制
• 集成终端阻抗电路
• 支持对端检测功能
• 支持LFPS发送与接收
• 支持最高5000ppm 扩频发送与接收
• 宽范围参考时钟频率
• 无需外接元器件
• 眼图检测机制
• ESD性能: HBM/MM >2000V/200V

• 支持多通道应用
• 完全兼容PIPE3接口协议
• PCIE模式下支持支持2.5G，5G 数据率
• USB3.0模式下支持5G数据率
• SATA模式下可支持1.5G，3G，6G数据率
• Support 1.5 G, 3.0 G and 6.0G serial data  rate in SATA application
• 并行数据总线可选择为40/32/20/16
• 可支持宽范围参考时钟
• 小数分频锁相环设计，可精确控制输出频率
• 锁相环失锁指示机制
• 与PCIE/USB3 协议规范兼容的低功耗模式选择
• 对端检测功能
• 支持扩频发送与扩频接收，最高5000ppm
• OOB/Beacon 发送与检测机制
• 可编程的预加重与去加重发送机制
• 与PCIE，USB3及SATA 电气规范完全兼容

• 下一代高清视频传输接口，低电磁干扰
• 0.45Gbps to 3Gbps 连续可调数据率范围
• 同时兼容 CML and LVDS 传输结构
• 同时兼容 AC 耦合与DC 耦合
• 低功耗设计，支持多通道应用
• 单通道面积小于0.1mm2, 包括IO PAD
• 支持0-6dB 可调节预加重
• 支持扩频发送
• 最高可支持16发送通道
• 内建自测机制
• 支持BGA，QFN，QFP封装
• ESD 性能: HBM 6000V / IEC 6000V

• LVDS收发器支持400Mbps – 2.5Gbps 单通道数据率
• 可支持16 路发送与接收通道，共享锁相环单元
• 输出摆幅可调节至最小280mV 以降低电磁干扰
• 支持-55C – 155C 宽温工作范围
• 可支持抗辐噪应用
• 内置并串转换单元
• 热插拔保护电路
• 可连接至背板，铜缆及光口
• 内置8B/10B 编解码单元
• 内置COMMA检测单元
• 内置锁相环模块
• 可设置低功耗模式
• 信号丢失检测电路
• 内建自测单元
• 2.5V或3.3V单电源供电
• 无需任何外接器件

• 支持16GT 8GT 5GT 2.5GT 数据率

• 符合PCI Express 4.0、3.1、2.1、1.1和 PIPE 4.2 标准

• x1、x2、x4、x8、x16多通道配置

• 多抽头自适应可编程连续时间线性均衡器（CTLE）和判决反馈均衡（DFE）

• 支持L1 SUB低功耗模式状态

• 支持SRIS

• 内置自检向量、PRBS生成和检查机制

• 温度范围-40℃-125℃

• 支持Flip chip倒装芯片封装

 VeriSilicon’s Power Management Platform offers Ultra Low Power LDOs, DCDCs, Battery Charger, System ON/OFF Control, Fault detection and so on. Each LDO, DCDC output voltage and power on sequence can be configurable. The whole PMU solution are silicon verified on 22nm, 40nm, 55nm, 90nm, 110nm process nodes.

 The C/D Combo PHY TX IP can be flexibly configured as DPHY or CPHY, which offers a compatibility with the DPHY only design, and a more cost-effective and power-efficiency design with CPHY. With CPHY V1.0 the maximum channel rate achieved would be 3Gsps which would result in an effective data rate of 6.85Gbps.CPHY reuses the similar Low power signaling same as the DPHY. CPHY is designed such a way that it can co-exist sharing the same lines as DPHY. CPHY/DPHY combo IPs will be compatible to operate on the same channels used by DPHY, which offer a much wider area of application and flexibility. It can work with both old DPHY systems and is compatible with new CPHY.

 The C/D Combo PHY TX IP can be flexibly configured as DPHY or CPHY, which offers a compatibility with the DPHY only design, and a more cost-effective and power-efficiency design with CPHY. With CPHY V1.0 the maximum channel rate achieved would be 3Gsps which would result in an effective data rate of 6.85Gbps.CPHY reuses the similar Low power signaling same as the DPHY. CPHY is designed such a way that it can co-exist sharing the same lines as DPHY. CPHY/DPHY combo IPs will be compatible to operate on the same channels used by DPHY, which offer a much wider area of application and flexibility. It can work with both old DPHY systems and is compatible with new CPHY.

 This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. Data lane0 supports HS support and ULPS in the forward direction, and supports LP Escape modes (LPDT, Trigger, ULPS) and Turnaround in both forward and reverse direction; Other Data lanes support HS and LP Escape modes(LPDT, Trigger, ULPS) in the forward direction. Each lane supports 2.5Gbps in High-Speed mode and 10Mbps/lane in Low-Power escape mode. The target applications are CSI-2 host and DSI device physical layers.

 This is a DPHY Master IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. Each data lane can support HS and LP Escape modes (LPDT, Trigger, ULPS) in forward direction. The supported data rate per lane is 2.5Gbps in High-Speed mode and 10Mbps in Low-Power escape mode. Only data lane0 is bi-directional and can additionally support Turnaround and LP Escape mode (LPDT and Trigger) in reverse direction. The target applications are CSI-2 device and DSI host physical layers.

 This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.1/v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes. It can support both Master and Slave side. Each lane supports 2.5Gbps in High-Speed mode and 10Mbps/lane in Low-Power escape mode. The target applications are CSI-2 and DSI physical layers.

 The USB3.0 PHY IP is designed according to the USB 3.0, USB2.0 Specification. It supports the USB3.0 5Gbps Super-Speed mode and backward compatibles with the USB2.0 480Mbps High-Speed, 12Mbps Full-Speed, and 1.5Mbps Low-Speed modes The USB 3.0 PHY interface complies with PHY Interface for PCI Express and USB3.0 Architectures specification (PIPE 3.0) and the USB2.0 PHY interface complies with the UTMI v1.05 specification.

 The USB 2.0 PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full/Low-Speed USB analog front-end with a build-in 8-bit/16-bit parallel interface. It is optimized for portable applications with low power dissipation while active and/or standby, and small area for low cost. The USB 2.0 PHY can be implemented as a discrete or integrated physical layer interface for any OTG device that complies with the On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification, or any host or peripheral that complies with the USB 2.0 specification. It also supports battery charging function.

 The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution. The LVDS Receiver IP converts the LVDS data stream back into 35 bits of CMOS data with a variety of LCD panel controllers.

 The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display with up to UXGA resolution.