This PLL IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By proper configurations to different values according to different FREF, CLK will be locked at the multiples of input frequency. CLKO is CLK divided by DP.

 This 1-lane to 4-lane PCIE PHY includes all high-speed analog functions for high-speed data transport between chips over PCBs and high quality cables. It can support different data rates (2.5Gbps to 8Gbps) for compatible with PCIe1.1, PCIe2.1 and PCIe3.1 protocols. It is optimized for low power operation and is suitable for 8b, 10b, 16b, 20b input data path width.

 The SD/EMMC PHY IP supports up to 208MHz which compliant with SDIO and EMMC specification. The SDIO/EMMC PHY includes DLL/Delay lines and IO. I/O input voltage is 3.3V, and signal voltage is within 3.3V/1.8V. Delay line supports dual data rate for DDR50, and single data rate for SDR104.

 This Video DAC specifies a 3-channel 10-bit resolution, high performance, low power CMOS Digital-to-Analog Converter (DAC) which offers exceptional direct current and alternating current performance and supports update rate up to 240MSPS with a stand-by mode to reduce the power dissipation.

 The analog-to-digital converter is a differential high speed low power IP which uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The ADC includes a core internal SAR ADC which consists of sample/hold circuits, a capacitive DAC, a comparator and logic control circuits.

 This digital-to-analog converter implements segmented R-2R and thermometer decoder architecture to achieve 12-bit resolution. The DAC consists of input data latch, control logic and resistor ladder offers single-ended or differential voltage output by a build-in analog buffer amplifier. The DAC support data update rate up to 1Msps and offer power-down mode to reduce power dissipation.

 This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.

 This audio codec integrates 2-channel 24-bit sigma-delta ADCs and 2-channel 24-bit sigma-delta DACs, and fractional audio PLL to support a wide range of sample rates. The input paths support stereo FM/LINE input, two analogue and two digital microphones. The output paths support stereo line output and stereo headphone output. It is suitable for low power portable audio applications.

 VeriSilicon's Vivante DeWarp Processor provides high-performance DeWarp processing for the correction of the distortion that is introduced in images produced by fisheye and wide-angle lenses. It is implemented with a line/tile-cache based architecture. With configurable address mapping look up tables and per tile processing, it can successfully generate corrected output images.

 VeriSilicon's Vivante ISP8200 Series ISP is designed for products requiring the processing of multiple camera streams with highter performance, particularly in automotive, AR/VR and industrial markets. It supports up to 8 real-time cameras, delivering 1.6 gigapixel per second throughput and produces ultra-high resolution, high-quality, accurate imaging, and colors. The support on multiple real-time camera operation and the latest sensor technology provides for flexible deployment in complex settings.

 The ISP8000Pico offers smaller silicon footprint with ultra-low power image processing as well as pixel processing and conversion to produce output data in low power applications. It supports up to 1080p camera sensor through the industry standard DVP interface. VeriSilicon's Vivante ISP8000Pico can perform frame rate and resolution control and produces useful output formats including RGB, YUV, RAW and Monochrome, which can be directly consumed by downstream IP blocks. Overall system power is kept at the minimum level during operations, and thus is. suitable for an always-on power domain designed to produce continuous output and the lowest power. ISP8000Pico has the industry-leading PPA (Performance, Power, Area) in its class and is targeted for wearable, AIoT and any battery-powered devices.

 As an industry-leading full camera ISP IP, VeriSilicon's Vivante Image Signal Processor (ISP) features sophisticated pixel processing for wearable device, smart home, video surveillance and automotive applications. The ISP8000 series is one of the most efficient RTL based implementations for high performance real-time image processing. It features low gate count per chip area, low power consumption, as well as higher throughput while at the same time lower memory requirements. Based on silicon-proven design, the ISP provides a minimal risk solution for integrating high performance image signal processor into silicon products.

 ZSPNano+ is a small, energy efficient, Digital Signal Processor Core for high performance Voice/Audio/Wireless applications. The compiler friendly architecture offers an orthogonal instruction set that greatly simplifies programming complex DSP algorithms and control code, with compact code density.

 ZSPNano is the perfect choice for Always ON applications involving sound detection, voice quality enhancement and command recognition. It is a tiny, energy efficient Digital Signal Processor Core for any MCU+DSP application. The compiler friendly architecture offers an orthogonal instruction set that greatly simplifies programming complex DSP algorithms and control code, with compact code density.