The LLI Controller connects two chips together to create a single “virtual chip”, with both chips sharing the same memory. This is achieved by the low latency from the “companion” chip to the memory interface of the host chip.

 The MIPI Alliance was created to define and promote open standards for interfaces to mobile application processors. The UniPro (Unified Protocol) is one in a family of standard addressing the mobile market. UniPro is a high speed interface technology for interconnecting integrated circuits in mobile phones or compatible products. The targeted scenario for UniPro technology is to connect chips (such as application processor to a peripheral device) within a mobile terminal.

 To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open standards for interfaces to mobile application processors. The Unified Protocol (UniPro) is one in a family of standards addressing the mobile market.

 To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open standards for interfaces to mobile application processors. The HSI (High Speed Synchronous Serial Interface) is one in a family of standard addressing the mobile market.

 The High Speed Synchronous Serial Interface (HSI) Controller is used to provide high bandwidth, point-to-point, serial communication between two peers, like the cellular modem and application processor on a mobile platform, such as a smartphone or a tablet. The Arasan HSI Controller IP is designed to provide MIPI HSI 1.00 compliant connectivity to a SoC.

 The Total MIPI Soundwire IP Solution enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code validated for compliance with the standard, a comprehensive test environment & compliance suite for validation of the IP, a Sound wire hardware development kit for FPGA prototyping and interoperability testing, a Sound wire protocol analyzer and the complete Soundwire software stack.

 The Total MIPI Soundwire IP Solution enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code validated for compliance with the standard, a comprehensive test environment & compliance suite for validation of the IP, a Soundwire hardware development kit for FPGA prototyping and interoperability testing, a Soundwire protocol analyzer and the complete Soundwire software stack.

 Arasan’s Serial Low-Power Inter-chip Media bus protocol (SLIMbus®) software stack provides developers a method for easy development, integration, and validation of system software. The SLIMbus software stack is operating system/processor agnostic and provides a generic set of APIs to the functional driver which abstracts the SLIM protocol-specific functionality. The software stack supports a variety of function drivers such as SPI, UART, BT, I2S, I2C, DAC, ADC, and Flash which make use of this generic API set to communicate on the common bus. APIs include commonly used device operations such as initialization, device configuration, data transfer, power management, and registration of call back for interrupt handling.

 Arasan’s SLIMbus® (Serial Low-power Inter-chip Media bus protocol) Hardware Validation Platform provides the mobile industry a versatile means to assist in the development and debugging of SLIMbus® products. By emulating a real-world SLIMbus host component, this platform can be used by system and software developers to completely validate the implementation of the SLIMbus interface in their products during various stages of the development cycle.

 The MIPI SLIMbus Host v2.0 typically resides in a mobile platform’s application processor and provides two-wire, multipurpose connectivity with multiple audio and another low/mid bandwidth peripheral devices. The Arasan SLIMbus Host Controller IP is designed to provide MIPI SLIMbus 2.0 compliant connectivity to an SoC.

 The Arasan SLIMbus v2.0 Device Controller IP is designed to provide MIPI SLIMbus compliant connectivity for a peripheral device, like an audio codec, to a SLIMbus compliant host, like an Applications Processor on a mobile platform, and share the bus bandwidth with other SLIMbus devices that may exist.

 Mobile radio communication is trending towards complex multi-radio systems comprising several transceivers. Arasan supports the latest MIPI RFFE standard v3.0 controller IP. The MIPI RFFE bus is a 2-wire serial interface that utilizes a bus frequency of up to 52 MHz and timing accurate trigger mechanisms to allow control of timing-critical functions. It is used to connect a digital RFIC to RF front end components, like Power Amplifiers, Low-Noise Amplifiers, and Antenna Sensors, which are considered RFFE Slaves.

Mobile radio communication systems are complex multi-radio systems comprising several transceivers. Arasan supports the latest MIPI RFFE standard v3.0. The RFFE bus is a 2-wire serial interface that utilizes a bus frequency of up to 52 MHz and timing accurate trigger mechanisms to allow control of timing-critical functions. It is used to connect a digital RFIC to RF front end components, like Power Amplifiers, Low-Noise Amplifiers, and Antenna Sensors, which are considered RFFE Slaves.

 The MIPI I3C host interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compatibility. This standard offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems.

 The Arasan I3C Device IP Core Implements Device functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is used for various sensors in the mobile/automotive system where an I3C Host transfers data and controls information between itself and various sensor devices. The I3C Device Controller IP Core can be easily integrated into the Sensor/Device devices with minimal gate count.