The I3C Total IP in a box HDK gives I3C SoC developers all the resources they need to implement MIPI I3C specifications right out of the box. The HDK contains I3C Master and Slave FPGA Boards programmed with Arasan’s I3C Master & Slave IP respectively, I3C software stacks and reference schematics. The HDK will also be compatible with open-source I3C drivers. Arasan’s I3C IP Cores are fully configurable across multiple parameters through simple scripts making it suitable for a variety of Sensor applications. Arasan’s I3C IP has been validated at the RTL with multiple I3C VIP vendors and the System Level at MIPI Interoperability Sessions with participation from the major companies actively implementing the I3C specifications. This ensures Arasan’s I3C IP is interoperable with multiple vendor solutions and is compliant to the specifications.
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I3C Device Controller IP Controller
The Arasan I3C Slave Controller IP Core Implements Slave functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is used for various sensors in the mobile/automotive system where an I3C Master transfers data and control information between itself and various sensor devices. The I3C Slave Controller IP Core can be easily integrated into the Sensor/Slave devices with minimal gate count.
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I3C HCI Host Controller
The MIPI I3C Host IP interface is an evolutionary standard that improves upon the features of I2C while maintaining backward compatibility. This standard offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems.
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DSI Receiver Controller
The Arasan DSI v1.3 Receiver Controller IP is designed to provide MIPI DSI 1.3 compliant high-speed serial connectivity for device (mobile display modules) with Type 1 to 4 architectures. Serial connectivity to the mobile applications processor’s DSI host is implemented using 1 to 4 D-PHY’s (also available from Arasan), depending on display bandwidth needs. This IP connects to the D-PHYs through the PPI interface.
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DSI v1.3 Transmit IP Core
The Arasan DSI Tx Controller IP is designed to provide MIPI DSI 1.3 – compliant high-speed serial connectivity for the host (mobile application processor) using 1 to 4 D-PHYs depending on bandwidth needs. Serial connectivity to the display module’s DSI device is implemented using 1 to 4 D-PHY’s (also available from Arasan), depending on display bandwidth needs. This IP connects to the D-PHYs through the PPI interface.
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MIPI DSI-2 Receiver IP Controller Core
The Arasan MIPI Display Serial Interface (DSI-2) Receiver (display panel interface) Controller IP provides a high-speed serial interface between an application processor and display modules using either MIPI C-PHY v1.1 or MIPI D-PHY v1.2 and v2.0.
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MIPI DSI-2 Transmitter IP Controller Core
The Arasan MIPI Display Serial Interface (DSI-2) Transmitter (host processor interface) Controller IP provides a high-speed serial interface between an application processor and display modules using either MIPI C-PHY v1.1 or MIPI D-PHY v1.2 and v2.0.
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Mipi CSI 2 V1.2 to V2.1
The MIPI®Alliance the Camera Serial Interface (CSI-2) dates back to November 2005 and was in widespread use in consumer devices by 2009. CSI-2 V1.1 was approved in January 2013. CSI-2 v1.2 was released in September 2014. The updated version, CSI-2 v1.3 (covered in this document) was released in February 2015.
Demand for increasingly higher image resolutions is pushing the bandwidth capacity of existing host processor-to-camera sensor interfaces. Common parallel interfaces are difficult to expand, require many interconnects and consume relatively large amounts of power. Emerging serial interfaces address many of the shortcomings of parallel interfaces while introducing their own problems. Incompatible, proprietary interfaces prevent devices from different manufacturers from working together. This can raise system costs and reduce system reliability by requiring “hacks” to force the devices to interoperate. The lack of a clear industry standard can slow innovation and inhibit new product market entry.
CSI-2 provides the mobile industry a standard, robust, scalable, low-power, high-speed, costeffective interface that supports a wide range of imaging solutions for mobile devices.
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Arasan MIPI CSI-2 V2.1 Transmitter IP Core
The Arasan MIPI CSI-2 Transmitter IP Core functions as a MIPI Camera Serial Interface between a peripheral device (display module) and a host processor (baseband, application engine). The Arasan MIPI CSI-2 Transmitter IP provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.
Pixel Data received from over the Camera Sensor Bus is packed into bytes by the Transmitter IP. The packing of the pixel into bytes follows the CSI-2 specification and based on the pixel format support. This IP calculates and appends an ECC/CRC value to a short packet (or) to the header of a long packet. Selection of ECC/CRC to the header is done based on the PHY connected. For the payload of a long packet carrying pixel data, this IP calculates its CRC value and appends it to the packet as a Packet Footer (PF). The packet is buffered in a FIFO and sent to one or more D-PHY/C-PHY depending on the lane distribution scheme set by the camera sensor/user.
Arasan MIPI CSI-2 Transmitter is compliant with MIPI CSI-2 specification v2.1 and supports DPHY v2.1 and the MIPI C-PHY v1.2.
Arasan offers the C-PHY in a combination configuration that supports both C-PHY interfaces and D-PHY interfaces. Our implementation makes efficient use of the high frequency signally pins for a minimal overhead to support both physical interfaces.
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Arasan MIPI CSI-2 V2.1 Receiver IP Core
The Arasan MIPI CSI-2 Receiver IP Core functions as a MIPI Camera Serial Interface Receiver, between a peripheral device (Camera module) and a host processor (baseband, application engine). The Arasan MIPI CSI-2 Receiver IP provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.
Arasan MIPI CSI-2 Receiver is compliant with MIPI CSI-2 v2.1 specification and supports DPHY v2.1 and the MIPI C-PHY v1.2.
Arasan offers the C-PHY in a combination configuration that supports both C-PHY interfaces and D-PHY interfaces. Our implementation makes efficient use of the high frequency signally pins for a minimal overhead to support both physical interfaces.
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Arasan MIPI CSI-2 Transmitter IP Core
The Arasan MIPI CSI-2 Transmitter IP Core functions as a MIPI Camera Serial Interface between a peripheral device (display module) and a host processor (baseband, application engine). The Arasan MIPI CSI-2 Transmitter IP provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.
Pixel Data received from over the Camera Sensor Bus is packed into bytes by the Transmitter IP. The packing of the pixel into bytes follows the CSI-2 specification and based on the pixel format support. This IP calculates and appends an ECC/CRC value to a short packet (or) to the header of a long packet. Selection of ECC/CRC to the header is done based on the PHY connected. For the payload of a long packet carrying pixel data, this IP calculates its CRC value and appends it to the packet as a Packet Footer (PF). The packet is buffered in a FIFO and sent to one or more D-PHY/C-PHY depending on the lane distribution scheme set by the camera sensor/user.
Arasan MIPI CSI-2 Transmitter is compliant with MIPI CSI-2 specification v2.1 and supports DPHY v2.1 and the MIPI C-PHY v1.2.
Arasan offers the C-PHY in a combination configuration that supports both C-PHY interfaces and D-PHY interfaces. Our implementation makes efficient use of the high frequency signally pins for a minimal overhead to support both physical interfaces.
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Arasan MIPI CSI-2 Receiver IP Core
The Arasan MIPI CSI-2 Receiver IP Core functions as a MIPI Camera Serial Interface Receiver, between a peripheral device (Camera module) and a host processor (baseband, application engine). The Arasan MIPI CSI-2 Receiver IP provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.
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MIPI C-PHY℠ v2.0 + D-PHY℠ v2.5 Combo IP Core
Arasan Chip Systems, the leading provider of IP for MIPI Standards, presents its latest MIPI C/D-PHY Combo IP.
This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and power dissipation, and is available for a range of foundry processes. This IP delivers 6 Gbps per lane for a max throughput of 24 Gbps in D-PHY℠ mode, and 6 Gsps per trio for a max throughput of 41.04 Gbps in C-PHY℠ mode. The C/D-PHY IP interfaces seamlessly to both D-PHY℠ and C-PHY℠ based sensors over its MIPI CSI-2® IP Core and MIPI Displays are increasingly adopting C-PHY over our MIPI DSI-2℠ IP core.
This combo PHY provides a low-power and high-performance interface for platforms ranging from processors to peripheral devices for mobile, automotive, AI, and IoT applications. It inter-operates seamlessly with Arasan Chip Systems CSI-2® and DSI-2℠, and offers built-in test capabilities including PRBS generator and internal loopback to support cost-effective tests for high volume manufacturing.
This combo PHY may be configured as either a D-PHY℠ with one clock and up to four data lanes, or a C-PHY℠ with up to 3 trio lanes. Area overhead to support both modes is minimized by reusing the D-PHY℠ blocks and high-speed IO’s.
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MIPI D-PHY℠ v2.5 IP Core
Arasan Chip Systems, the leading provider of IP for MIPI Standards, presents its latest MIPI C/D-PHY Combo IP.
This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and power dissipation, and is available for a range of foundry processes. This IP delivers 6 Gbps per lane for a max throughput of 24 Gbps in D-PHY℠ mode, and 6 Gsps per trio for a max throughput of 41.04 Gbps in C-PHY℠ mode. The C/D-PHY IP interfaces seamlessly to both D-PHY℠ and C-PHY℠ based sensors over its MIPI CSI-2® IP Core and MIPI Displays are increasingly adopting C-PHY over our MIPI DSI-2℠ IP core.
This combo PHY provides a low-power and high-performance interface for platforms ranging from processors to peripheral devices for mobile, automotive, AI, and IoT applications. It inter-operates seamlessly with Arasan Chip Systems CSI-2® and DSI-2℠, and offers built-in test capabilities including PRBS generator and internal loopback to support cost-effective tests for high volume manufacturing.
This combo PHY may be configured as either a D-PHY℠ with one clock and up to four data lanes, or a C-PHY℠ with up to 3 trio lanes. Area overhead to support both modes is minimized by reusing the D-PHY℠ blocks and high-speed IO’s.
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MIPI M-PHY® 4.1 Analog Transceiver
MIPI M-PHY Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a minimum of two unidirectional lanes along with associated lane management logic. Each of the M-PHY lanes consists of a lane module (M-TX) that communicates to a corresponding module (M-RX) on the other chip via a serial interconnect that consists of two differential lines. The differential lines can carry both High-Speed (HS) and Low-Speed (LS) signals.
Arasan’s M-PHYs is of Type 1, which apply to UFS, LLI, and CSI-3 protocols. The Multi-gear M-PHY 4.1 consists of analog transceivers, high-speed PLL, data recovery units as well as state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant with the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
Arasan follows a rigorous practice of co-verifying the controllers and their corresponding PHY’s to ensure that they operate together as intended. These, together with Arasan’s software stacks, are mapped onto Arasan’s Hardware Validation Platforms, which are used for early compatibility and interoperability testing with the corresponding host/device platforms from Arasan and a number of MIPI contributor members. This minimizes end-to-end compatibility risk for customers.
