The C/D-PHY HDK is build using Arasan’s TSMC 12nm Fin-FET C/D-PHY ASIC. Future generations of the HDK will use Arasan’s TSMC 7nm Fin-FET C/D-PHY ASIC.

The HDK supports C-PHY v2.0 with speeds up to 6 Gsps per trio & D-PHY v2.5 with speeds up to 6 Gbps per lane. This HDK enables customers to prototype their C/D-PHY based projects using Arasan’s MIPI CSI-2 or DSI-2 IP controller cores and software stacks.

Host and Device components are connected by a serial link employing the MIPI® Alliance C/D-PHY standard.

This platform is used for Functional Testing

• CSI-2/DSI-2 -Tx to CSI-2/DSI-2 -Rx Video transfers
• Static images
• Motion Video
• 1/2/3 Lane traffic

and MIPI – CSI-2/DSI-2 Protocol Testing

• Using 3rd party MIPI traffic generators
• Agilent Protocol Tester/Analyzer.
• Moving pixel Protocol Tester.

 The MIPI CPHY V1.1 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock. It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0). The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires. This is different from the two-wire differential “lane” used in D-PHY.

C-PHY was designed to coexist on the same IC pins as D-PHY so that dual-mode devices could be developed with low power signaling similar to DPHY. Arasan’s CPHY-DPHY combination provides a 3 channel MIPI CPHY v1.1.

Symbol encoding effectively transfers 2.286 bits per symbol compared to 1.0 bits per lane for D-PHY. This version of C-PHY (v1.1) operates at 2.5GHz(2.5GS/s), the same as the D-PHY V1.2(2.5Gb/s).

A 3 channel C-PHY provides 17Gbps which enables:

• 4K video at 60fps

1080p at 240fps (for cool slow-motion videos)

 The MIPI C-PHY V1.2 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock. It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0). The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires. This is different from the two-wire differential “lane” used in D-PHY.

C-PHY was designed to coexist on the same IC pins as D-PHY so that dual-mode devices could be developed with low power signaling similar to DPHY. Arasan’s CPHY-DPHY combination provides a 3 channel C-PHY v1.2 and a four-lane D-PHY v1.2 in a single IP core. This allows a seamless implementation allowing the interface to D-PHY based sensors or C-PHY based sensors.

Symbol encoding effectively transfers 2.286 bits per symbol compared to 1.0 bits per lane for D-PHY. The C-PHY (v1.2) operates at 3GS/s, whereas the D-PHY V1.2 (2.5Gb/s).

A four-lane D-PHY V1.2 provides 10Gbps which enables:

• 4K video at 30fps
• 1080p at 120fps

A 3 channel C-PHY V1.2 provides 17Gbps which enables:

• 4K video at 60fps
• 1080p at 240fps (for cool slow-motion videos)

 The Next Generation of CSI, DSI, and D-PHY: A webinar recorded July 9, 2014

To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI®) Alliance was created to define and promote open standards for interfaces to mobile application processors. D-PHY is the physical layer specified for several of the key protocols within the MIPI® family of specifications.

Arasan offers the industry’s broadest portfolio of foundry and process technology support for MIPI D-PHY. The MIPI D-PHY analog IP is available in foundry processes spanning 28nm to 180nm. Arasan specializes in porting Analog Transceiver IP Cores to new foundry processes.

Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant with the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols at speeds up to 1.5Gbps per lane. It is a Universal PHY that can be configured as a transmitter, receiver, or transceiver. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions.

 Arasan’s MIPI® D-PHY compliant to the MIPI D-PHY Specification v2.1 supports:

This specification is primarily intended to define a solution for a bit-data rate range of:

• 80 to 1500 Mbps per Lane without de-skew calibration
• up to 2500 Mbps with de-skew calibration,
• up to 4500 Mbps with equalization.

When the DUT implementation supports a data rate greater than 1500 Mbps, it shall also support de-skew capability. When a PHY implementation supports a data rate more than 2500 Mbps, it shall also support equalization, and Spread Spectrum Clocking shall be available.

Arasan D-PHY IP Core is seamlessly integrated with Arasan’s MIPI CSI IP and DSI IP Controller Cores.

Arasan offers industry’s broadest portfolio of foundry and process technology support for MIPI D-PHY. The MIPI D-PHY IP is available in foundry processes spanning 7nm to 180nm. Arasan specializes in porting Analog Transceiver IP Cores to new foundry processes.

Arasan’s MIPI® D-PHY IP Core is fully compliant to the D-PHY specification version 2.1. It provides a point to point connection between master and slave or host and device that comply with a relevant MIPI®

 MIPI M-PHY Specification Version 3.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a minimum of two unidirectional lanes along with associated lane management logic. Each of the M-PHY lanes consists of a lane module (M-TX) that communicates to a corresponding module (M-RX) on the other chip via a serial interconnect that consists of two differential lines. The differential lines can carry both High-Speed (HS) and Low-Speed (LS) signals.

High Density TCAM, Peri LVT

Contact ROM

10TSRAM

6T SRAM

6TSRAM

6TSRAM

10-Track