The INNOSILICON DDR IPTM Mixed-Signal PSRAM  PHY provides turnkey physical interface solutions for ICs requiring access to  JEDEC compatible PSRAM devices. It is optimized for low power and high speed  applications with robust timing and small silicon area. It supports APmemory  UHS PSRAM components in the market. The PHY components contain PSRAM  specialized functional and utility IO devices, critical timing synchronization  module (TSM), the low-jitter PLL, the TX and RX logic control for the PSRAM  interface.

 The INNOSILICON DDR IPTM Mixed-Signal  DDR3/3L/2/LPDDR3/2 Combo PHYs provide turnkey physical interface solutions for  ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low  power and high speed applications with robust timing and small silicon area. It  supports all JEDEC DDR3/3L/2/LPDDR3/2 SDRAM components in the market. The PHY  components contain LPDDR specialized functional and utility high performance  I/Os, critical timing synchronization module (TSM) and a low power/jitter DLLs  with programmable fine-grain control for any SDRAM interface.

 The INNOSILICON DDR IPTM Mixed-Signal  DDR4/3/3L/LPDDR4/4X/3 Combo PHYs provide turnkey physical interface solutions  for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for  low power and high speed applications with robust timing and small silicon  area. It supports all JEDEC DDR4/3/3L/LPDDR4/4X/3 SDRAM components in the  market. The PHY components contain DDR specialized functional and utility I/Os,  critical timing synchronization module (TSM) and a low power/jitter DLLs with  programmable fine-grain control for any SDRAM interface.

 The INNOSILICON DDR IPTM Mixed-Signal  LPDDR5/5X/4/4X Combo PHYs provide turnkey physical interface solutions for ICs  requiring access to JEDEC compatible SDRAM devices. It is optimized for low  power and high speed applications with robust timing and small silicon area. It  supports all JEDEC LPDDR5/4 SDRAM components in the market. The PHY components  contain DDR specialized functional and utility high performance I/Os, critical  timing synchronization module (TSM) and a low power/jitter DLLs with  programmable fine-grain control for any SDRAM interface.

The INNOSILICON DDR IPTM Mixed-Signal  DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring  access to JEDEC compatible SDRAM devices. It is optimized for low power and  high speed applications with robust timing and small silicon area. It supports  all JEDEC DDR5/4 SDRAM components in the market. The PHY components contain DDR  specialized functional and utility high performance I/Os, critical timing  synchronization module (TSM) and a low power/jitter DLLs with programmable  fine-grain control for any SDRAM interface.

 Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive  amounts of low-latency data to pass seamlessly between smaller chips as if they  were all on the same bus. Chiplets, defined as independent functional blocks  making up a large chip, are pivotal in this new era of heterogeneous  integration to achieve performance and efficiency gains. Based on this,  Innosilicon launches the INNOLINK™ chiplet solution as  a critical enabler of the power- and cost-efficient die-to-die (D2D),  chip-to-chip (C2C), board-to-board (B2B) and package-to-package (P2P)  connectivity for data center, networking, 5G, HPC and AI applications.

 The third-generation HBM (HBM2e/3) technology, outlined by the JESD235C standard, inherits physical 128-bit DDR interface with 2n/4n prefetch architecture, internal organization, 1024-bit input/output, 1.2 V I/O and core voltages as well as all the crucial parts in the original technology. Just like the predecessor, HBM2e/3 supports two, four, eight or twelve DRAM devices on a base logic die (2Hi, 4Hi, 8Hi, 12Hi stacks) per KGSD. HBM Gen 3 expands the capacity of DRAM devices within a stack to 24GB and increases the data rate by up to 7.2Gb/s per pin. In addition, the new technology brings an important improvement to bandwidth maximization.

 Graphics Double Data Rate (GDDR) is a modern type of Synchronous Graphics Random-Access Memory (SGRAM) with a high bandwidth DDR interface designed for use in graphics cards, game consoles, and high-performance computing. GDDR6/6X are currently the highest-bandwidth GDDR memory solutions, capable of supporting increased per-pin bandwidth (up to 21Gbps for GDDR6X, 16Gbps for GDDR6), lower operating voltages (1.35V), higher performance and lower power consumption compared to GDDR5/GDDR5X.

 FDSOI 28nm

TSMC 16nm

 TSMC 65nm GP

 TSMC 65nm GP